The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to a process and structure for forming a metal oxide semiconductor field effect transistor (MOSFET) implementing thin sidewall spacer geometries.
FIGS. 1(a)–1(e) depict cross-section views of a portion of a semiconductor device manufactured in accordance with conventional processing techniques. As shown in FIG. 1(a), a semiconductor device 10 is formed on a wafer. The device includes a substrate 12 and a patterned gate stack 15 formed thereon. Each patterned gate stack 15 may be formed of a gate material such as polycrystalline silicon, for example, and as conventionally known, the gate 15 is formed on a thin gate dielectric layer 20 previously formed on top of the substrate 12. Prior to the formation of low resistivity cobalt, titanium, or nickel silicide contacts with active device regions 16, 18 and gate 15 of the semiconductor device 10, thin nitride spacers are first formed on each gate sidewall. Typically, as shown in FIG. 1(a), a dielectric etch stop layer 25, ranging from about 10 Å–300 Å in thickness, but preferably 50 Å–150 Å, is first deposited on the thin gate oxide layer 20 over the substrate surfaces and the patterned gate stack 15. While this dielectric etch stop prevents recessing of the substrate during reactive ion etching (RIE) of the spacer, it has the disadvantage of being susceptible to removal or undercut during the extensive preclean that must be utilized prior to silicide formation.
Then, as shown in FIG. 1(b), an additional dielectric layer 30 is deposited on the patterned gate stack and active device regions. This additional dielectric layer is typically formed of a nitride material.
While this dielectric etch stop prevents recessing of the substrate during spacer RIE, it has the disadvantage of being susceptible to removal or undercut during the extensive pre-clean that must be utilized prior to silicide formation.
As shown in FIG. 1(c), a RIE process is performed, resulting in the formation of vertical nitride spacers 35a, 35b on each gate wall. Prior to metal deposition, which may be titanium, cobalt or nickel, a lengthy oxide strip process is performed to prepare the surface for the silicide formation. This oxide strip is crucial to achieving a defect free silicide. However, as illustrated in FIG. 1(d), the problem with this lengthy oxide strip is that the dielectric etch stop beneath the spacers 25 becomes severely undercut at regions 40a, 40b. The resultant oxide loss or undercut gives rise to the following problems: 1) the barrier nitride layer 50 that is ultimately deposited, as shown in FIG. 1(e), will be in contact with the gate dielectric edge 17, thus degrading gate dielectric reliability; 2) the silicide in the source/drain regions 60a,b (not shown) may come into contact with the gate dielectric at the gate conductor edge, which would create a diffusion to gate short); and, 3) the degree of undercut will vary significantly from lot to lot. These aforementioned problems are particularly acute for transistors with the thin spacer geometries required for (which becoming continued CMOS scaling.
Thin sidewall spacer geometries are becoming increasingly important aspects of high performance MOSFET design. Thin spacers allow the silicide to come into close proximity to the extension edge near the channel, thereby decreasing MOSFET series resistance and enhancing drive current. The implementation of a spacer etch process (specifically RIE) benefits substantially from an underlying dielectric layer (typically oxide) beneath the nitride spacer film. This dielectric serves as an etch stop for the nitride spacer RIE. Without this etch stop in place, the spacer RIE would create a recess in the underlying substrate, degrading the MOSFET series resistance, and in the case of thin SOI substrates, reducing the amount of silicon available for the silicide process.
In order to avoid the problems associated with thin spacer geometries on thin SOI, it would be extremely desirable to provide a method for avoiding the oxide undercut when performing the oxide removal step during the pre-silicide clean.